vpsFree.cz


by snajpa

Oct. 8, 2019, 11:42 p.m.

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diff --git a/versa_ecp5.py b/versa_ecp5.py
index c11b3af..cb39fb0 100755
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -29,6 +29,8 @@ from liteeth.core import LiteEthUDPIPCore
 
 from litescope import LiteScopeAnalyzer
 
+from litesdcard.emulator import SDEmulator, _sdemulator_pads
+
 # DDR3TestCRG --------------------------------------------------------------------------------------
 
 class DDR3TestCRG(Module):
@@ -272,6 +274,29 @@ class EthernetSoC(BaseSoC):
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
         self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
 
+# SDEmuSoC -------------------------------------------------------------------------------------
+class SDEmuSoC(EthernetSoC):
+    csr_map = {
+        "sdemulator": 20
+    }
+    csr_map.update(EthernetSoC.csr_map)
+
+    interrupt_map = {
+    }
+    interrupt_map.update(EthernetSoC.interrupt_map)
+
+    mem_map = {
+        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+    }
+    mem_map.update(EthernetSoC.mem_map)
+
+    def __init__(self, eth_port=0, **kwargs):
+        EthernetSoC.__init__(self, **kwargs)
+
+        # SD Emulator
+        sdcard_pads = _sdemulator_pads()
+        self.submodules.sdemulator = SDEmulator(self.platform, sdcard_pads)
+
 # BISTSoC --------------------------------------------------------------------------------------
 class BISTSoC(EthernetSoC):
     csr_map = {
@@ -303,6 +328,8 @@ def main():
         soc = BaseSoC(toolchain=toolchain)
     elif "ethernet" in sys.argv[1:]:
         soc = EthernetSoC(toolchain=toolchain)
+    elif "sdemu" in sys.argv[1:]:
+        soc = SDEmuSoC(toolchain=toolchain)
     elif "bist" in sys.argv[1:]:
         soc = BISTSoC(toolchain=toolchain)
     else: